Multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security ID, and many other applications. Incorporating MTP memories nonetheless also typically comes at the expense of some additional processing steps.
For example, some of the existing approaches to constructing MTP memories require additional masking steps to achieve sufficiently high junction breakdown voltage (BV). Also, some of the existing approaches result in MTP memories having large cell sizes due to design rule requirements. In order to achieve smaller cell sizes, multiple un-proven sub-design rule techniques have to be applied.
Accordingly, it is desirable to provide a simple and cost-free MTP structure to create memory cells with the standard complementary metal oxide semiconductor (CMOS). Further, it is desirable to provide a method for fabricating an improved MTP memory cell. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.